The present invention relates to a semiconductor device, especially a structure of a semiconductor substrate which composes the device substrate and in which semiconductor elements are formed, and to the separation of such elements. The present invention also relates to a semiconductor device of various kinds ranging from a logic integrated circuit device (herein called a logic IC) a memory integrated circuit device (herein called a memory IC), to a photo sensor integrated circuit device (herein called a photo sensor IC) and to an integrated circuit including a bipolar transistor and an MOS transistor (herein called an BiMOSIC).
Conventionally, a single Si semiconductor substrate is formed by crystal growth in accordance with the Czochralski method (herein called a CZ substrate) which is used for forming elements of a logic IC comprising CMOS (called a CRMOSIC) and a memory IC. FIG. 24 is a cross section showing a conventional general CMOSIC formed on this CZ substrate, wherein a deep diffusion region 242 is provided on a surface of a CZ substrate 243 and wherein the substrate 243 and the diffusion region 242 each contain an N-type transistor 244 and a P-type transistor 241, respectively.
As well, for forming a memory IC such as DRAM, a part of photo sensor IC such as CCD and BiCMOSIC, a semiconductor substrate (called a CZ epi substrate) having an epitaxial layer (called an epi layer) on a CZ substrate is used. This epitaxial layer is formed by epitaxial growth of Si. Therefore the decline of yield due to the defects of the semiconductor substrate can be prevented. This is because the epi layer contains only a small amount of oxygen, a cause of such defects, which are generated during heat treatment in the manufacturing process and then combined with Si.
FIG. 25 is a schematic cross section of a general DRAM cell formed on a CZ epi substrate, which shows a conventional integrated circuit device. As seen in FIG. 25, a switch transistor 255 and a condenser 256 are formed on a surface of an epitaxial layer 252. FIG. 26 is a schematic cross section of a general BiCMOSIC in which an NPN bipolar transistor 262, a CMOS device 260, and a LDMOS transistor 261 are formed on a CZ epi substrate, which shows a conventional integrated circuit device.
For forming a PIN diode and a photodiode, or a photodiode array arranging several photodiodes and a photosensor such as a photovoltaic cell represented by a solar battery, a single Si semiconductor substrate (it is herein called an FZ substrate) which is formed by crystal growth in accordance with zone melting method is occasionally used. This is because an FZ substrate has higher electric resistivity than that of a CZ substrate.
For forming a PIN diode, an avalanche photodiode (herein called an APD), and a photodiode or a photosensor IC such as a photodiode array arranging several photodiodes and BiCMOSIC, a semiconductor substrate (herein called an FZ epi substrate) having an epitaxial layer (herein called an epi layer) which is produced by epitaxial growth of Si is occasionally used. This is because an FZ substrate lowers a series resistance as well as the fact that an epi layer provides a high electric resistivity. When BiCMOSIC is formed with an FZ substrate, separation of elements is achieved.
FIG. 27 is a schematic cross section showing an APD formed on a conventional FZ epi substrate. As seen in FIG. 27, a P-type epitaxial layer 271 (called Tv layer) in which impurity concentration is under 10.sup.14 atoms/cm.sup.3 is provided and furthermore, on its surface, a P.sup.+ -type diffusion region 277 and a N.sup.+ -type diffusion region 274 are provided. The substrate 272 and the N.sup.+ -type diffusion region 274 includes an anode electrode 276 and a cathode electrode 273 respectively.
In case of forming a photovoltaic cell and so on, if output by several elements connected in series is needed since electric power generation for one piece of PN junction is insufficient, as shown in FIG. 29, a substrate (herein called a dielectric isolation substrate) formed by the dielectric isolation method is used.
For example, as shown in FIG. 29(a), firstly a V-groove 292 is formed on a N-type Si substrate 291 and then a SiO.sub.2 film 293 which will be an isolation insulator by thermal oxidation is formed on the surface of the substrate. Next, poly Si is formed for several hundreds of gm so that a poly Si substrate 294 is made. Next, the Si substrate 291 is polished until the Si substrate is divided with the V-groove 292 so that a P.sup.+ -layer 295, a N.sup.+ -layer 296, and an electrode 297 are formed as shown in FIG. 29(b).
A conventional semiconductor device has a semiconductor substrate of which the structure is stated above. However, there are some problems to be solved as mentioned below.
The first problem is as follows:
As shown in FIG. 24, when a CZ substrate is used, its resistivity to latch-up caused by a parasitic thyristor comprising, for example, a P-type impurity source region 245, a N-type impurity well region 242, a P-type CZ semiconductor wafer region 243, and an N-type impurity drain region 246 is low. A memory IC such as DRAM having a CMOS structure has a similar problem. As stated above, it is a common problem to all of IC that defects increase, namely, yield lowers, by educed oxygen, which is characteristic of a CZ substrate.
The educed oxygen increases the number of recombination centers in a forbidden energy region which is for recombination of electron and hole. That lowers carrier lifetime. As a result, that further causes fatal problems, for charge retention time of a memory declines in DRAM and photoelectric conversion efficiency and carrier transfer efficiency worsens in CCD.
The second problem is as follows.
As shown in FIG. 25, when a CZ epi substrate is used, if substrate resistivity of a CZ substrate 251 is, for example, a predetermined amount .OMEGA.-cm, lower than an upper epi layer 252, the problem of latch-up stated above is almost solved. However, since oxygen educes from the CZ substrate including relatively much oxygen to the epi layer in manufacturing process, though the epi layer includes little oxygen in general, increase of defects or increase of recombination centers in a forbidden energy region for recombination of an electron with a hole, both of which are caused by educed oxygen, lower carrier lifetime of an inversion layer 253, as stated above. It is not expected that radiation resistance rises remarkably. As shown in FIG. 26, the CZ substrate includes a CMOS section 260 and so has the problems stated above. Specifically, for example, in case of a LD (Lateral Diffusion) MOS section which requires higher breakdown voltage, namely, high electric resistivity, an N-type epi layer 263 cannot acquire high electric resistivity because of the CZ when it is formed on the P-type CZ substrate 251.
Owing to the decline of carrier lifetime, the NPN bipolar transistor section 262 and so on cannot achieve a good bipolar property. Furthermore, BiCMOSIC has many manufacturing processes, is complicated, and costs much to produce.
The third problem is as follows:
When a FZ substrate is used, though hidden from the view, the problem caused by the educed oxygen is considerably solved. However, an FZ substrate has a problem in physical strength because oxygen concentration of such a substrate is low. Namely, a substrate is deformed (a wafer is warped) by heat treatment in manufacturing process and dislocation slip increases. Once a substrate is warped it gets hard to advance following manufacturing process. The larger a wafer size, the more a substrate becomes warped. As for latch-up and radiation resistance, the conventional substrate cannot be improved.
The fourth problem is as follows:
When an FZ epi substrate is used, warping is inevitable though latch-up is improved, which is hidden from view. FIG. 28 shows a schematic impurity concentration distribution of a semiconductor layer at the section A-A' of FIG. 27. The epitaxial layer 271 is constituted of epitaxial silicon, so it cannot have very high electric resistivity. Furthermore, the epitaxial layer 271 cannot be formed thickly. A FZ epi can have a higher electric resistivity than a CZ substrate, but several hundred .OMEGA.-cm is the limit.
A thickness of epi is a few dozen .mu.m generally. It is at most 100 .mu.m. In order to detect X-rays by an avalanche photodiode ("APD"), the P.sup.+ -type layer 272 is a scattering region of an incident ray. The length a of that region should be short. However, for example, even if a substrate having an epi layer is polished from the back in order to thin the substrate, because a P.sup.- -type layer having high impurity concentration must remain in order to lower contact resistance with an anode electrode, a region b remains. Therefore the substrate cannot be thinned more than a certain extent. The region b is a diffusion region of impurity from a substrate in epitaxial growth. At the very least, the region b having a profile sloped gently occupies a few .mu.m.
The fifth problem is as follows:
When a dielectric isolation substrate is used, it takes too long and costs too much to manufacture the dielectric isolation substrate because it has so many complex manufacturing processes as stated before. Furthermore, the wafer size cannot be large because of the manufacturing process. It follows that the dielectric isolation substrate cannot be manufactured by the latest manufacturing process.